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512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 1 - rev. 1.1 august 2010 18mb ddrii+ sram specification * samsung electronics reserves the right to c hange products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply. 165 fbga with pb & pb-free (rohs compliant)
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 2 - rev. 1.1 august 2010 document title 512kx36-bit, 1mx18-bit ddr tm ii+ cio b2 sram the attached data sheets are prepared and approved by samsung el ectronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to yo ur requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 1.0 1.1 remark final final history 1. first release 1. corrected the timing diagram of cl2.5 on page.15 2. corrected package dimensions on page.19 draft date aug. 28, 2008 aug. 10, 2010
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 3 - rev. 1.1 august 2010 512kx36-bit, 1mx18-bit ddrii cio b2 sram features functional block diagram ? 1.8v+0.1v/-0.1v power supply. ? dll circuitry for wide output data valid window and future freg- uency scaling. ? i/o supply voltage 1.5v+0.1v/-0.1v ? pipelined, double-data rate operation. ? common data input/output bus . ? hstl i/o ? full data coherency, providing most current data. ? synchronous pipeline read with self timed late write. ? read latency : 2.5 clock cycles ? registered address, control and data input/output. ? ddr(double data rate) interface on read and write ports. ? fixed 2-bit burst for both read and write operation. ? clock-stop supports to reduce current. ? two input clocks(k and k ) for accurate ddr timing at clock rising edges only. ? two echo clocks (cq and cq ) to enhance output data traceability. ? data valid pin(qvld) supported ? single address bus. ? byte write (x18, x36) function. ? simple depth expansion with no data contention. ? programmable output impedance(zq). ? jtag 1149.1 compatible test access port. ? 165fbga(11x15 ball aray fbga) with body size of 15x17mm ld address r/w doff data reg clk gen ctrl logic 512kx36 (1mx18) memory array write driver k k bw x 4(or 2) dq select output control sense amps write/read decode output reg output select output driver notes : 1. numbers in ( ) are for x18 device 18 18 (or 19) 36 (or 18) 36 72 (echo clock out) cq, cq 36 (or 18) ddr sram and double data rate comprise a new family of products developed by cypress, renesas, idt, nec and samsung technology. (or 19) (or 18) (or 36) 36 (or 18) * -f(e)c(i) f(e) [package type] : e-pb free, f-pb c(i) [operating temperature] : c-commercial, i-industrial organiza- tion part number cycle time access time unit x36 k7k1636u2c-f(e)c(i)45 2.22 0.45 ns k7k1636u2c-f(e)c(i)40 2.5 0.45 ns k7k1636u2c-f(e)c(i)33 3.0 0.45 ns x18 K7K1618U2C-f(e)c(i)45 2.22 0.45 ns K7K1618U2C-f(e)c(i)40 2.5 0.45 ns K7K1618U2C-f(e)c(i)33 3.0 0.45 ns add reg qvld
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 4 - rev. 1.1 august 2010 pin configurations (top view) k7k1636t2c(512kx36) notes : 1. * checked no connect(nc) pins are reserved for higher d ensity address, i.e. 3a for 36mb, 10a for 72mb, 2a for 144mb . 2. bw 0 controls write to dq0:dq8, bw 1 controls write to dq9:dq17, bw 2 controls write to dq18:dq26 and bw 3 controls write to dq27:dq35. 1 2 3 4 5 6 7 8 9 10 11 a cq nc / sa* nc/sa* r/w bw 2 k bw 1 ld sa nc / sa* cq b nc dq27 dq18 sa bw 3 kbw 0 sa nc nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qvld sa sa nc dq9 dq0 r tdo tck sa sa sa nc sa sa sa tms tdi pin name notes: 1. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 2. not connected to chip pad internally. 3. k, k can not be set to v ref voltage. symbol pin numbers description note k, k 6b, 6a input clock qvld 6p q valid output cq, cq 11a, 1a output echo clock doff 1h dll disable sa 9a,4b,8b,5c,7c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs dq0-35 2b,3b,11b,3c,10c,11c,2d,3d,11d,3e,10e,11e,2f,3f 11f,2g,3g,11g,3j,10j,11j,3k,10k,11k,2l,3l,11l 3m,10m,11m,2n,3n,11n,3p,10p,11p data inputs outputs r/w 4a read, write control pin, read active when high ld 8a synchronous load pin, bus cycle sequence is to be defined when low bw 0 , bw 1, bw 2 , bw 3 7b,7a,5a,5b block write control pin,active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 1 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply ( 1.8 v ) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply ( 1.5 ) v ss 4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l, 4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 2a,10a,1b,9b,10b,1c,2c,6c,9c,1d,9d,10d,1e,2e,9e, 1f,9f,10f,1g,9g,10g,1j,2j,9j,1k,2k,9k 1l,9l,10l,1m,2m,9m,1n,9n,10n,1p,2p,9p,6r no connect 2
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 5 - rev. 1.1 august 2010 pin configurations (top view) k7k1618t2c(1mx18) notes: 1. * checked no connect(nc) pins are reserved for higher density address, i.e. 10a for 36mb and 2a for 72mb. 2. bw 0 controls write to dq0:dq8 and bw 1 controls write to dq9:dq17. 1 2 3 4 5 6 7 8 9 10 11 a cq nc / sa* sa r/w bw 1 k nc ld sa nc/sa* cq b nc dq9 nc sa nc k bw 0 sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qvld sa sa nc nc dq0 r tdo tck sa sa sa nc sa sa sa tms tdi pin name notes: 1. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 2. not connected to chip pad internally. 3. k, k can not be set to v ref voltage. symbol pin numbers description note k, k 6b, 6a input clock qvld 6p q valid output cq, cq 11a, 1a output echo clock doff 1h dll disable sa 3a,9a,4b,8b,5c,7c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs dq0-17 2b,11b,10c,3d,3e,11e,2f,11f,3g,10j,3k,11k,2l,11l 10m,3n,3p,11p data inputs outputs r/w 4a read, write control pin, read active when high ld 8a synchronous load pin, bus cycle sequence is to be defined when low bw 0 , bw 1 7b, 5a block write control pin,active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 1 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply ( 1.8 v ) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply ( 1.5v ) v ss 4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l,4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 2a,7a,1b,3b,5b,9b,10b,1c,2c,3c,6c,9c,11c,1d,2d,9d,10d 11d,1e,2e,9e,10e,1f,3f,9f,10f,1g,2g,9g,10g,11g 1j,2j,3j,9j,11j,1k,2k,9k,10k,1l,3l,9l,10l 1m,2m,3m,9m,11m,1n,2n,9n,10n,11n,1p,2p,9p,10p,6r no connect 2
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 6 - rev. 1.1 august 2010 the k7k1636t2c and k7k1618t2c are 18,874,368-bits ddr common i/o synchronous pipelined burst srams. they are organized as 524,288 words by 36bits for k7k1 636t2c and 1,048,576 words by 18 bits for k7k1618t2c . address, data inputs, and all control signals ar e synchronized to the input clock ( k or k ). read data are referenced to echo clock ( cq or cq ) outputs. read address and write address are registered on rising edges of the input k clocks. common address bus is used to access address both for read and write operations. the internal burst counter is fixed to 2-bit sequential for both read and write operations. synchronous pipeline read and late write enable high speed operations. simple depth expansion is accomplished by using ld for port selection. byte write operation is supported with bw 0 and bw 1 ( bw 2 and bw 3) pins for x18 ( x36 ) device. ieee 1149.1 serial boundary scan (jtag) simplifies monitoriing package pads attachment status with system. the k7k1636t2c and k7k1618t2c are implemented with samsung's high performanc e 6t cmos technology and is available in 165pin fbga packages. multip le power and ground pins minimize ground bounce. general description read operations read cycles are initiated by initiating r/w as high at the rising edge of the positive input clock k. address is presented and stored in the read address register sync hronized with k clock. for 2-bit burst ddr operation, it will access two 36-bit or 18-bit data words with each read command. the first pipelined data is transfered out of the device triggered by k clock rising edge. next burst data is triggered by the rising edge of following k clock rising edge. continuous read operations are init ated with k clock rising edge. and pipelined data are transferred out of device on every rising edge of both k and k clocks. initial read data latency is 2.5 clock cycles when dll is on. when the ld is disabled after a read operation, the k7k1636t2c and k7k1618t2c will first complete burst read operation before entering into deselect mode at the next k clock rising edge. then output drivers disabled autom atically to high impedance state. write cycles are initiated by activating r/w as low at the rising edge of the positive input clock k. address is presented and stored in the write addres s register synchronize d with next k clock. for 2-bit burst ddr operation, it will write two 36- bit or 18-bit data words with each write command. the first "late writed" data is transfered and registered in to the device synchronous with next k clock rising edge. next burst data is transfered and r egistered synchronous with following k clock rising edge. continuous write operations are initated with k rising edge. and "late writed" data is presented to the device on every rising edge of both k and k clocks. when the ld is disabled, the k7k1636t2c and k7k1618t2c will enter into deselect mode. the device disregards input data presented on the same cycle r/w disabled. the k7k1636t2c and k7k1618t2c support byte write operations. with activating bw 0 or bw 1 ( bw 2 or bw 3 ) in write cycle, only one byte of input data is presented. in k7k1618t2c, bw 0 controls write operation to d0:d8, bw 1 controls write operation to d9:d17. and in k7k1636t2c, bw 2 controls write operation to d18:d26, bw 3 controls write operation to d27:d35. write operations
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 7 - rev. 1.1 august 2010 programmable impedance output buffer operation depth expansion the designer can program the sram's output buf fer impedance by terminating the zq pin to v ss through a precision resistor(rq). the allowable range of rq is between 175 ? and 350 ? . the value of rq (within 15%) is five times the output impedance desired. for example, 250 ? resistor will give an output impedance of 50 ? . impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. in all cases impedance updates are transparent to t he user and do not produce ac cess time "push-outs" or other anomalous behavior in the sram. to guarantee optimum output driver impedance after power up, the sram needs 1024 non-read cycles. each port can be selected and deselected independently with r/w be shared among all srams and provide a new ld signal for each bank. before chip deselected, all read and write pending operations are completed. echo clock operation to assure the output tracibility, the sram provides the output echo clock, pair of compliment clock cq and cq , which are synchronized with inte rnal data output. echo clocks run free during normal operation. the echo clock is triggered by internal ou tput clock signal, and transfered to external through same structures as output drive r. the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. power-up/power-down supply voltage sequencing output valid pin (qvld) the q valid indicates valid output data. qvld is activated half cycle before the read data for the receiver to be ready for cap turing the data. qvld is edge aligned with cq and cq .
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 8 - rev. 1.1 august 2010 detail specification of power-up sequence in ddrii+ sram ddrii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. ? power-up sequence 1. apply power and keep doff at low state (all other inputs may be undefined) - apply vdd before vddq - apply vddq before vref or the same time with vref 2. just after the stable power and clock(k,k ), take doff to be high. 3. the additional 2048 cycles of cl ock input is required to lock the dll after enabling dll * notes : if you want to tie up the doff pin to high with unstable clock, then y ou must stop the clock for a few seconds (min. 30ns) to reset the dll after it become a stable clock status. ? dll constraints 1. dll uses k clock as its synchronizing input, the i nput should have low phase jitter wh ich is specified as tk var . 2. the lower end of the frequency at which the dll can operate is 120mhz. 3. if the incoming clock is unstable and the dll is enabled, then the dll may lock onto a wrong frequency and this may cause the failure in the initial stage. status power-up k,k * notes : when the operating frequency is changed, dll reset should be required again. after dll reset again, the minimum 2048 cycles of clock inpu t is needed to lock the dll. ~ ~ unstable clkstage 2048 cycle ~ ~ dll locking range any command power up & initialization sequence (doff pin fixed high, clock controlled) k,k ~ ~ min 30ns v dd v ddq v ref doff v dd v ddq v ref ~ ~ ~ ~ 2048 cycle ~ ~ status power-up unstable clkstage dll locking range any command stop clock ~ ~ inputs clock must be stable ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ power up & initialization sequence (doff pin controlled) inputs clock must be stable
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 9 - rev. 1.1 august 2010 write truth table (x18) notes: 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( ). 3. assumes a write cycle was initiated. 4. this table illustates operation for x18 devices. k k bw 0 bw 1 operation l l write all bytes ( k ) l l write all bytes ( k ) l h write byte 0 ( k ) l h write byte 0 ( k ) h l write byte 1 ( k ) h l write byte 1 ( k ) h h write nothing ( k ) h h write nothing ( k ) write truth table (x36) notes: 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( ). 3. assumes a write cycle was initiated. k k bw 0 bw 1 bw 2 bw 3 operation l l l l write all bytes ( k ) l l l l write all bytes ( k ) l h h h write byte 0 ( k ) l h h h write byte 0 ( k ) h l h h write byte 1 ( k ) h l h h write byte 1 ( k ) h h l l write byte 2 and byte 3 ( k ) h h l l write byte 2 and byte 3 ( k ) hhhh write nothing ( k ) hhhh write nothing ( k ) truth tables synchronous truth table notes: 1. x means "don t care". 2. the rising edge of clock is symbolized by ( ). 3. before enter into clock stop status, all pending read and write operations will be completed. k ld r/w dq operation dq(a1) dq(a2) stopped x x previous state previous state clock stop h x high-z high-z no operation lhq out at k(t+2) q out at k (t+2) read l l din at k(t+1) din at k (t+1) write
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 10 - rev. 1.1 august 2010 absolute maximum ratings note: 1. stresses greater than those listed under "absolute maximum ra tings" may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operat ing sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.5 to 2.9 v voltage on v ddq supply relative to v ss v ddq -0.5 to v dd v voltage on input pin relative to v ss v in -0.5 to v dd+ 0.3 v storage temperature t stg -65 to 150 c operating temperature commercial / industrial t opr 0 to 70 / -40 to 85 c storage temperature range under bias t bias -10 to 85 c operating conditions (0 c t a 70 c) note: 1. v ddq must not exceed v dd during normal operation. 2. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 3. v il (min)dc= - 0.3v, v il (min)ac=-1.5v(pulse width 3ns). 4. v ih (max)dc= v ddq +0.3v, v ih (max)ac= v ddq +0.85v(pulse width 3ns). 5. overshoot : v ih (ac) v ddq +0.5v for t 50% t khkh (min). undershoot : v il (ac) v ss -0.5v for t 50% t khkh (min). 6. this condition is for ac function test only, not for ac parameter test. 7. to maintain a valid level, the transitioning edge of the input must : a) sustain a constant slew rate from the current ac level through the target ac level, v il(ac) or v ih(ac) b) reach at least the target ac level c) after the ac target level is reached, continue to maintain at least the target dc level, v il(dc) or v ih(dc) parameter symbol min typ max unit supply voltage v dd 1.7 1.8 1.9 v v ddq 1.4 1.5 1.6 v reference voltage v ref 0.7 0.75 0.8 v input low voltage(dc) 2,3) v il(dc) -0.3 - v ref -0.1 v input high voltage(dc) 2,4) v ih(dc) v ref +0.1 - v ddq +0.3 v input high voltage(ac) 6,7) v il(ac) v ref + 0.2 - - v input low voltage(ac) 6,7) v ih(ac) --v ref - 0.2 v
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 11 - rev. 1.1 august 2010 dc electrical characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes: 1. minimum cycle. i out =0ma. 2. |i oh |=(v ddq /2)/(rq/5) 15% for 175 ? rq 350 ? . |i ol |=(v ddq /2)/(rq/5) 15% for 175 ? rq 350 ? . 3. minimum impedance mode when zq pin is connected to v dd . 4. operating current is calculated with 100% read cyc les or 100% write cycles. 5. standby current is only after all pending read and write burst opeactions are completed. 6. programmable impedance mode. parameter symbol test conditions min max unit notes input leakage current i il v dd =max ; v in =v ss to v ddq -2 +2 a output leakage current i ol output disabled, -2 +2 a operating current (x36): qdr i cc v dd =max , i out =0ma cycle time t khkh min -45 - 950 ma 1,4 -40 - 900 -33 - 800 operating current (x18): qdr i cc v dd =max , i out =0ma cycle time t khkh min -45 - 850 ma 1,4 -40 - 800 -33 - 700 standby current(nop): qdr i sb1 device deselected, i out =0ma, f=max, all inputs 0.2v or v dd -0.2v -45 - 400 ma 1,5 -40 - 350 -33 - 300 output high voltage v oh1 v ddq /2-0.12 v ddq /2+0.12 v 2,6 output low voltage v ol1 v ddq /2-0.12 v ddq /2+0.12 v 2,6 output high voltage v oh2 i oh =-1.0ma v ddq -0.2 v ddq v3 output low voltage v ol2 i ol =1.0ma v ss 0.2 v 3
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 12 - rev. 1.1 august 2010 ac timing characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes : 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control signals are r/ w and ld . however bw x does not apply to this parameters. bw x signals obey the data setup and hold times. 3. to avoid bus contention, at a given voltage and temperature tklz is bigger than tkhz. the specs as shown do not imply bus contenti on because tklz is a min parameter that is worst case at totally di fferent test conditions (0 c, 1.9v) than tkhz, which is a max parameter(worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 4. clock phase jitter is the variance fr om clock rising edge to the next expected clock rising edge. 5. vdd slew rate must be less than 0.1v dc per 50 ns for dll lock retention. dll lock time begins once vdd and input clock are stable. 6. this parameter is extrapolated from the input timing parameters (t khk h - 200ps where 200ps is the internal jitter.) this parameter is only guaranteed by design and not tested in production. parameter symbol -45 -40 -33 unit note min max min max min max clock clock cycle time (k, k )t khkh 2.22 8.4 2.5 8.4 3.0 8.4 ns clock phase jitter (k, k )t k var 0.20 0.20 0.20 ns 4 clock high time (k, k )t khkl 0.4 0.4 0.4 ns clock low time (k, k )t klkh 0.4 0.4 0.4 ns clock to clock (k k ) t khk h 0.95 1.06 1.3 ns dll lock time (k) t k lock 2048 2048 2048 cycle 5 k static to dll reset t k reset 30 30 30 ns output times k, k high to output valid t khqv 0.45 0.45 0.45 ns k, k high to output hold t khqx -0.45 -0.45 -0.45 ns k, k high to echo clock valid t khcqv 0.45 0.45 0.45 ns k, k high to echo clock hold t khcqx -0.45 -0.45 -0.45 ns cq, cq high to output valid t cqhqv 0.2 0.2 0.2 ns cq, cq high to output hold t cqhqx -0.2 -0.2 -0.2 ns cq high to cq high t cqhcq h 0.75 0.86 1.1 ns 6 k, k high to output high-z t khz 0.45 0.45 0.45 ns k, k high to output low-z t klz -0.45 -0.45 -0.45 ns cq, cq high to qvld valid t qvld -0.2 0.2 -0.2 0.2 -0.2 0.2 ns setup times address valid to k rising edge t avkh 0.40 0.40 0.40 ns control inputs valid to k rising edge t ivkh 0.40 0.40 0.40 ns 2 data-in valid to k, k rising edge t dvkh 0.28 0.28 0.28 ns hold times k rising edge to address hold t khax 0.40 0.40 0.40 ns k rising edge to control inputs hold t khix 0.40 0.40 0.40 ns k, k rising edge to data-in hold t khdx 0.28 0.28 0.28 ns
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 13 - rev. 1.1 august 2010 thermal resistance note : junction temperature is a function of on-chip power dissipati on, package thermal impedance, mounting site temperature and mou nting site thermal impedance. t j =t a + p d x ja prmeter symbol typ unit notes junction to ambient ja 20.8 c /w junction to case jc 2.3 c /w junction to pins jb 4.3 c /w pin capacitance note : 1. parameters are tested with rq=250 ? and v ddq =1.5v. 2. periodically sampled and not 100% tested. prmeter symbol testcondition typ max unit notes address control input capacitance c in v in =0v 3.5 4 pf input and output capacitance c out v out =0v 4 5 pf clock capacitance c clk -34pf v ddq /2 50 ? sram zo=50 ? 0.75v v ref zq 250 ? ac test output load ac test conditions note : parameters are tested with rq=250 ? parameter symbol value unit core power supply voltage v dd 1.7~1.9 v output power supply voltage v ddq 1.4~1.6 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 0.3/0.3 ns output timing reference level v ddq /2 v
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 14 - rev. 1.1 august 2010 application inrormation sram#1 sa r/w bw 0 dq zq k sram#4 r vt r=50 ? vt=v ref vt r r=250 ? r=250 ? bw 1 k sa r/w ld 3bw 0 cq zq k bw 1 k dq address r/w ld bw return clk source clk return clk source clk memory controller ld 0 dq cq cq cq sram1 input cq sram1 input cq sram4 input cq sram4 input cq
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 15 - rev. 1.1 august 2010 nop k k sa 12 3 4 5 6 7 81012 11 ld read write 9 t khkh undefined don t care note 1. q 1-1 refers to output from address a 1 . q 1-2 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) two clock cycle after a nop . 3. two nop cycle is the mandatory and 3 rd nop cycle is not necessary for co rrect ddrii+ read/write operation. however at high clock frequencies, considering the delay of real system board condition, it may be required to prevent bus contention. t khk h t klkh r/w nop t khkl timing wave forms of read, write and nop nop write read nop nop nop (note3) dq cq cq qvld t ivkh t khix a 1 a 4 a 2 a 3 a 5 t qvld q1-1 q1-2 t khqv t khqx t khcqv d2-1 d2-2 d5-1 d5-2 q3-1 q3-2 q4-1 q4-2 read write a 6 t cqhqv
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 16 - rev. 1.1 august 2010 ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufac turing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg - ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up , therefore, trst signal is not required. it is possible to use th is device without utilizing the tap. to disable the tap control ler without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and ma y be left unconnected. but they may als o be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 reserved do not use 6 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 reserved do not use 6 1 1 1 bypass bypass register 4
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 17 - rev. 1.1 august 2010 id register definition note : part configuration /def=001 for 18mb, /wx=11 for x36, 10 for x18 /t=1 for dll ver., 0 for non-dll ver. /q=1 for qdr, 0 for ddr /b=1 for 4bit burst, 0 for 2bit burst /s=1 for separa te i/o, 0 for common i/o part revision number (31:29) part configuration (28:12) samsung jedec code (11: 1) start bit(0) 512kx36 000 00def0wx0t0q0b0s0 00011001110 1 1mx18 000 00def0wx0t0q0b0s0 00011001110 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bit 32 bits 107 bits 1mx18 3 bits 1 bit 32 bits 107 bits note : 1. nc pins are read as "x" ( i.e. don t care.) order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 10a 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 2a 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1h 85 1j 86 2j 87 3k 88 3j 89 2k 90 1k 91 2l 92 3l 93 1m 94 1l 95 3n 96 3m 97 1n 98 2m 99 3p 100 2n 101 2p 102 1p 103 3r 104 4r 105 4p 106 5p 107 5n 108 5r 109 internal order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e boundary scan exit order
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 18 - rev. 1.1 august 2010 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 1.7 1.8 1.9 v input high level v ih 1.3 - v dd +0.3 v input low level v il -0.3 - 0.5 v output high voltage(i oh =-2ma) v oh 1.4 - v dd v output low voltage(i ol =2ma) v ol v ss -0.4v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 11. parameter symbol min unit note input high/low level v ih /v il 1.8/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
512kx36 & 1mx18 dd rii+ cio b2 sram k7k1636u2c K7K1618U2C - 19 - rev. 1.1 august 2010 165 fbga package dimensions c side view 15mm x 17mm body, 1.0mm bump pitch, 11x15 ball array f b ? h g a bottom view top view b a d e e symbol value units note symbol value units note a 15 0.1 mm e 1.0 mm b 17 0.1 mm f 14.0 mm c 1.3 0.1 mm g 10.0 mm d 0.35 0.05 mm h 0.5 0.05 mm

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